Visualized Network-on-Chip (NoC) performance analysis

“Achronix’s latest Speedster7t FPGA devices based on TSMC’s 7nm FinFET process incorporate a revolutionary new two-dimensional network-on-chip (2D NoC). Like a highway network running on the FPGA programmable logic fabric, the 2D NoC provides ultra-high bandwidth for the data transmission of the FPGA external high-speed interface and the internal programmable logic.

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Author: Huang Lun, Senior Application Engineer at Achronix

1 Overview

Achronix’s latest Speedster7t FPGA devices based on TSMC’s 7nm FinFET process incorporate a revolutionary new two-dimensional network-on-chip (2D NoC). Like a highway network running on the FPGA programmable logic fabric, the 2D NoC provides ultra-high bandwidth for the data transmission of the FPGA external high-speed interface and the internal programmable logic.

As shown in Figure 1.

Figure 1 Speedster 7t FPGA block diagram

2. Advantages of 2D NoC to Speedster 7t FPGA

The growing demand for data acceleration puts forward higher and higher requirements for hardware platforms, and FPGAs play an increasingly important role as a programmable and customizable high-performance hardware. In recent years, high-end FPGAs have used more and more Hard IP to improve the data transmission bandwidth and memory bandwidth of the FPGA periphery. However, while the density of logic arrays continues to increase, the improvement of communication performance is not so obvious, so the exchange of data within the FPGA has increasingly become the bottleneck of data transmission.

Achronix sees this challenge as an opportunity to develop an entirely new architecture that eliminates the design challenges of traditional FPGAs and improves system performance. Achronix’s solution innovatively uses a revolutionary two-dimensional (2D) high-speed network-on-chip (NoC) on top of the traditional FPGA routing structure. The Speedster7t NoC connects to all on-chip high-speed interfaces: 400G Ethernet, PCIe Gen5, GDDR6, and multiple ports of DDR4/5.

3. Performance of 2D NoCs

The two-dimensional network-on-chip (2D NoC) on the Speedster 7t FPGA is not built by programmable logic, but implemented by solidified ASIC logic. The fixed operating frequency is 2GHz. The NoC uses a series of high-speed row and column network paths to distribute within the entire FPGA. data, thereby distributing data traffic horizontally and vertically throughout the FPGA fabric. Each row or column in the NoC has two 256-bit, unidirectional, industry-standard AXI lanes that can operate at 512 Gbps (256bit x 2GHz) transmission bandwidth in each direction. The total bandwidth is up to 27Tbps.

Figure 2 Speedster 7t FPGA NoC and Access Point NAP

In Speedster 7t’s two-dimensional network-on-chip, each cross-node has two network access points (NAPs), as shown in Figure 2, one is the master and the other is the slave. There are a total of 160 such access points throughout the device, which ensures that no matter where the logic is placed in the device, the tool can find the nearest NAP and bring it to the 2D network-on-chip. There will also be a delay in the transmission of data on the two-dimensional on-chip network. If the data does not pass the length of a grid, the delay will increase by 2~3 clock cycles, that is, 1~1.5ns (the clock is fixed at 2GHz, so one cycle is 0.5 ns).

It can be seen that the two-dimensional on-chip network brings a huge performance advantage to high-end FPGAs, but how to effectively use this advantage to bring substantial performance improvement to your application is very important.

4. How to plan the performance of 2D NoC more efficiently – Visual NoC performance analysis

Achronix provides a visual NoC performance analysis tool in the new version of ACE tool. Just import the simulation log file, you can intuitively see the bandwidth usage on NoC in different time slices, so that designers can better plan The location of the NAP balances the bandwidth utilization of the NoC, making it work more efficiently.

The tool is very simple to use, click in the ACE toolicon, you can enter the NoC Performance View page, click Browse on this page to import the simulated log file.

Figure 3 Import the simulation log file

On the right side of the NoC Performance View page there is a list of options that can Display the NoC occupancy under different conditions. The first option is to choose the displayed protocol, Flit or AXI. The second option is to choose which AXI Type to Display. The third option is to select Display Mode, Throughput Mode or Blockage Mode.

Figure 4 NoC Performance View Options

In Throughput mode, green represents high throughput, light blue represents medium throughput, and dark blue represents low throughput, as shown in Figure 5.

Figure 5 The throughput mode of NoC Performance View

In Blockage mode, red represents the highest congestion, yellow represents medium congestion, and green represents low congestion. As shown in Figure 6.

Figure 5 Blockage mode of NoC Performance View

Hover the colored part with the mouse in the picture, and the information in the specific log file corresponding to the picture will be displayed in the floating window, including the time point and which session.

Figure 6 Mouse hover display

Therefore, through the NoC Performance View tool, we can intuitively see the usage of the 2D on-chip network, where the utilization rate is relatively high and where the utilization rate is relatively low. According to this tool, we can more easily specify the logic that is more suitable for access. Click the NAP to connect to the network on chip, so that the two-dimensional network on chip can operate more efficiently.

Later, we will continue to understand the various features of Speedster 7t FPGA in depth, and will use some examples to illustrate how to use these features more efficiently, so stay tuned. For more information or any questions, you can contact us through the Achronix official account, or visit the Achronix official website http://www.achronix.com