“MAX120 is a new product recently introduced by MAXIM Company in the United States. It is a 12-bit analog-to-digital converter with sampling circuit produced by BICMOS process, and integrates track/hold (T/H) and precision power supply. Its conversion time is 1.6μs, the sampling rate is 500Ksps, the internal and external sampling modes are optional, the continuous conversion mode is optional, the input Voltage is ±5V, the limit value is ±15V, the power consumption is 210mW, there is no missing code at full temperature, and it can It is convenient to interface with general microprocessors, suitable for high-speed data acquisition and processing systems, and meets the requirements of high-speed and high-precision data processing.
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Authors: Gong Lanfang; He Jiabin;
MAX120 is a new product recently introduced by MAXIM Company in the United States. It is a 12-bit analog-to-digital converter with sampling circuit produced by BICMOS process, and integrates track/hold (T/H) and precision power supply. Its conversion time is 1.6μs, the sampling rate is 500Ksps, the internal and external sampling modes are optional, the continuous conversion mode is optional, the input voltage is ±5V, the limit value is ±15V, the power consumption is 210mW, there is no missing code at full temperature, and it can It is convenient to interface with general microprocessors, suitable for high-speed data acquisition and processing systems, and meets the requirements of high-speed and high-precision data processing.
The following briefly introduces the main pins and functions of the chip.
● MODE is the mode input terminal. When MODE=VDD, INT/BUSY is used as an interrupt signal; when MODE=OPEN or MODE=DGND, INT/BUSY is used as BUSY output;
● CONVST is the conversion start input terminal, and the conversion starts at the falling edge of the waveform;
● The output of INT or BUSY indicates the status of the converter;
● CS is the chip select terminal, low level is valid, when it is low level, three-state data output is allowed; when both CONVST and RD are low level, a conversion is started on the falling edge of CS.
● RD is read input terminal, low level is valid, when it is low level, three-state data output is allowed; when both CONVST and RD are low level, a conversion is started on the falling edge of RD.
Operating mode
The MAX120 has five operating modes.
● Full Control Mode (Mode 1): Provides the user with maximum control to control the start of conversion and fetch operations. The full control mode is used for the microprocessor system (μP) that inserts or cannot insert the wait state, and can interface with the bus of the DSP.
● Standalone mode (mode 2) and continuous conversion mode (mode 5): for systems without a processor, or for processor-based systems where the ADC and processor are buffered by a first-in-first-out (FIFO) It is usually not directly connected to the DSP if it is interfaced with a processor or direct memory access (DMA).
● Slow storage mode (mode 3): It is mainly used in systems where the processor can be forced into a waiting state during ADC conversion, and can interface with the DSP’s bus.
● ROM mode (mode 4): used in systems where the processor cannot be forced to enter a waiting state, and can interface with the DSP’s bus.
In these 5 operating modes, the start-up of the converter is controlled by one of 3 digital input signals (CONVST, RD or CS). In either mode, CONVST must be low to start a conversion, and once a conversion is entered, it cannot be started. The read operation is controlled by RD and CS. To read the output data, these two digital input signals must be low level, and the working state of the INT/BUSY output converter determines when the last conversion time is valid.
In addition, the mode input terminal MODE has the following provisions for the output of INT/BUSY:
If MODE=VDD, INT/BUSY is an interrupt signal. At this time, INT/BUSY is low level. After the conversion data is read, INT/BUSY returns to high level.
If MODE is open or connected to digital ground, INT/BUSY is output as BUSY. At this time, INT/BUSY becomes low level when the conversion starts, and rises to high level after conversion, and the data is valid at D0~D11.
MAX120 interface example
Generally, the analog signal must be buffered and amplified before the A/D conversion to reduce the impact on the A/D converter. This interface circuit uses the LF353 high-speed integrated operational amplifier to form a signal buffer amplifier, as shown in the figure.
The analog signal is input from the AIN terminal. CLKIN is the A/D conversion pulse input end of the A/D converter, this pulse signal is taken from the ALE end of the single-chip microcomputer, and the single-chip microcomputer can use 80c32. CONVST is connected to the P1.0 port of the microcontroller, and starts an A/D conversion on the falling edge of the pulse. The output of the data is controlled by chip selection CS and RD; Y0, Y1, Y2 are taken from the output end of the decoder connected to the microcontroller. Y0 and RD control the data output of the A/D converter. When Y0 is valid, the falling edge of RD outputs data, and the rising edge of RD is reversed by the Inverter as the input latch pulse of the latch 74F373. 12 bits of data are latched in 2 latches. Y1 and RD are used to control the lower 8-bit data in the read latch; Y2 and RD are used to control the upper 4-bit data in the read latch.
concluding remarks
There are many A/D conversion chips used in data acquisition systems, and their application fields are also relatively wide. As a new member of the A/D family, MAX120 continues the functions of existing products, and also has advantages in data acquisition speed and accuracy. It is very ideal as a data acquisition component in signal processing systems such as speech and noise and automatic control systems with high dynamic performance requirements.
The Links: 6MBI200FB-060 EPM570T100I5N MY-IGBT
