“Gallium nitride (GaN) transistors switch much faster than silicon MOSFETs, potentially enabling lower switching losses. However, specific package types limit the switching performance of GaN FETs when the slew rate is high. Integrating the GaN FET and driver in one package reduces parasitic inductance and optimizes switching performance.Integrated driver also implements protection functions
By: Yong Xie, Design Engineer, Texas Instruments; Paul Brohlin, Design and Systems Manager
Integrating GaN FETs with their drivers can improve switching performance and simplify GaN-based power stage designs.
Gallium nitride (GaN) transistors switch much faster than silicon MOSFETs, potentially enabling lower switching losses. However, specific package types limit the switching performance of GaN FETs when the slew rate is high. Integrating the GaN FET and driver in one package reduces parasitic inductance and optimizes switching performance.Integrated driver also implements protection functions
The switching performance of gallium nitride (GaN) transistors is better than that of silicon MOSFETs because gallium nitride (GaN) transistors have lower termination capacitance and avoid reverse recovery due to body diodes for the same on-resistance loss. It is because of these properties that GaN FETs can achieve higher switching frequencies, thereby increasing power density and transient performance while maintaining reasonable switching losses.
Traditionally, GaN devices have been packaged as discrete devices and driven by separate drivers because GaN devices and drivers are based on different processing technologies and may come from different vendors. Each package will have wire bonds and leads that introduce parasitic inductance, as shown in Figure 1a. These parasitic inductances cause switching losses, ringing, and reliability issues when switching at high slew rates of tens to hundreds of volts per nanosecond.
Integrating a GaN transistor with its driver (Figure 1b) eliminates common-source inductance and greatly reduces the inductance between the driver output and the GaN gate, as well as in the driver ground. In this article, we will examine the problems and limitations caused by package parasitics. Optimizing these parasitics within an integrated package reduces this problem and enables excellent switching performance with high slew rates above 100V/ns.
Figure 1. A GaN device driven by a driver in a separate package (a); an integrated GaN/driver package (b).
Figure 2. Simplified Diagram of Half-Bridge Circuit Used for Simulation
To simulate parasitic inductance effects, we used a depleted GaN half-bridge power stage in a direct drive configuration (Figure 2).We set up the half bridge as a buck converter with a bus Voltage of 480V and a 50% duty cycle with a dead time of 50ns (output voltage [VOUT] = 240V), and an Inductor current of 8A. This GaN gate is driven directly between switching voltage levels. A resistive drive sets the turn-on slew rate of the GaN device. A current source will only emulate an inductive load connected to the switch (SW) node in a continuous conduction mode buck converter.
Common source inductance
One of the most important parasitic elements in high-speed switching is the common-source inductance (Lcs in Figure 1a), which limits the slew rate at which the device can draw current. In a traditional TO-220 package, the GaN source flows from the bond wire to the lead, and both the sink current and the gate current flow from here. This common-source inductance modulates the gate-to-source voltage as the current drawn changes. Common source inductance can be higher than 10nH (including bond wires and package leads), limiting slew rate (di/dt) and increasing switching losses.
With the integrated package shown in Figure 1b, the driver ground is soldered directly to the source pad of the GaN die. This Kelvin source connection minimizes the common source inductance path shared by the power and gate loops, allowing the device to switch at a much higher current slew rate. A Kelvin source pin can be added to a discrete package; however, this extra pin makes it a non-standard power supply package. The Kelvin source pins must also be routed from the printed circuit board (PCB) back to the driver package, adding to the gate loop inductance.
Figure 3. High-pipe turn-on with different common source inductances: red = 0nH, green = 1nH, blue = 5nH. E_HS is the integrated value (energy consumption) of the VDS and IDS of the high-level device over the run time.
Figure 3 shows the hard switching waveforms when the high-level switch is turned on. At a common source inductance of 5nH, the slew rate is halved due to source derating effects. A lower slew rate results in longer transition times, resulting in higher cross-conduction losses, as shown in the power dissipation graph. At a common source inductance of 5nH, the energy loss increases from 53μJ to 85μJ, a 60% increase. Assuming a switching frequency of 100kHz, the power loss increases from 5.3W to 8.5W.
Gate loop inductance
The gate loop inductance includes the gate inductance and the driver ground inductance. The gate inductance is the inductance between the driver output and the GaN gate. When using a standalone package, the gate inductance includes the driver output bond wire (Ldrv_out), the GaN gate bond wire (Lg_gan), and the PCB trace (Lg_pcb), as shown in Figure 1a.
Depending on the package size, the gate inductance can range from a few nanohenries in a compact surface mount package (e.g. quad flat no-lead) to over 10nH in a leaded power package (e.g. TO-220). If the driver is integrated in the same leadframe as the GaN FET (Figure 1b), the GaN gate is soldered directly to the driver output, which reduces the gate inductance to below 1nH. Package integration can also greatly reduce the driver ground inductance (from Ldrv_gnd + Ls_pcb in Figure 1a to Lks in Figure 1b).
Reducing the gate loop inductance has a huge impact on switching performance, especially during turn-off where the GaN gate is pulled down by a resistor. The resistance value of this resistor needs to be low enough so that the device does not turn back on during switching due to the drain being pulled high. This resistor forms an inductor-resistor-capacitor (LRC) tank with the gate-source capacitance and gate loop inductance of the GaN device. The Q figure of merit in Equation 1 is expressed as:
At higher values of gate loop inductance, the Q factor increases and the ringing becomes higher. This effect was simulated using a 1Ω pull-down resistor to turn off the low-pass GaN FET, and in Figure 4 this effect occurred for 9.97µs, where the gate loop inductance varied from 2nH to 10nH. At 10nH, the low tube VGS produces 12V ringing below negative gate bias. This greatly increases the stress on the gate of the GaN transistor. One thing to note is that over stress on the gate of any FET can negatively impact reliability.
The gate loop inductance also has a huge impact on the turn-off retention capability. When the gate of the low tube device is held at the off voltage and the high tube device is turned on, the low tube drain capacitance delivers a large current into the hold loop of the gate. This current pushes the gate up through the gate loop inductance. This is illustrated by the curve change in Figure 4 at approximately 10.02µs. As the inductance increases, the low tube VGS is pushed higher, increasing the shoot-through current, which can be seen in the high tube leakage current graph (ID_HS). This shoot-through current increases the cross-conduction energy loss (E_HS) from 53µJ to 67µJ.
Figure 4. Low tube turn-off and high tube turn-on waveforms for different gate loop inductances: red = 2nH, green = 4nH, blue = 10nH. E_HS is executive energy consumption.
According to equation (1), one way to reduce gate stress is to increase the pull-down resistor value, which in turn reduces the Q factor of the LRC tank. Figure 5 shows the simulation results with a 10nH gate loop inductance and a pull-down resistor (Rpd) varying from 1Ω to 3Ω. Although the gate undershoot is limited to a few volts below the negative bias voltage by a 3Ω pull-down resistor, the off-retention capability deteriorates, resulting in higher shoot-through current. This is evident in the leakage current graph.
The E_HS energy plot shows an additional 13µJ loss per switching cycle, an almost 60% increase compared to 53µJ with a gate loop inductance of 2nH and a 1Ω pull-down resistor (Figure 4).
Assuming a switching frequency of 100kHz, the power loss on the high-pipe device increases from 5.3W to 8W due to shoot-through caused by high gate loop inductance and high pull-down resistor values. This additional power loss makes heat dissipation within the power device very unmanageable and increases packaging and cooling costs.
Figure 5. Simulation results using 10nH gate loop inductance and pull-down resistors: Rpd = 1Ω (red), 2Ω (green), and 3Ω (blue). E_HS is executive energy consumption.
To alleviate shoot-through voltage, the gate can be biased to a more negative voltage, but doing so increases the stress on the gate and increases dead-time losses when the device is in the third quadrant. Therefore, the trade-off between gate stress and device turn-off retention capability is difficult to manage when the gate loop inductance is relatively high. You have to increase gate stress, or allow half-bridge shoot-through, which increases cross-conduction losses and current loop ringing, and can lead to Safe Operating Area (SOA) issues. An integrated GaN/driver package provides low gate loop inductance and minimizes gate stress and shoot-through risk.
GaN device protection
Mounting the driver in the same leadframe as the GaN transistor ensures that their temperatures are relatively close, due to the excellent thermal conductivity of the leadframe. Thermal sensing and thermal protection can be placed inside the driver so that when the sensed temperature exceeds the protection limit, the GaN FET will turn off.
A series MOSFET or a parallel GaN sense FET can be used to perform overcurrent protection. They all require a low-inductance connection between the GaN device and its driver. Since GaN typically switches extremely fast with large di/dt, the extra inductance in the interconnect lines can cause ringing and require long blanking times to prevent current protection from failing. The integrated driver ensures that there are as few inductive connections as possible between the sensing circuit and the GaN FET, so that the current protection circuit can react as quickly as possible to protect the device from overcurrent stress.
Figure 6. SW node waveform when the high-pipe is turned on in a half-bridge buck converter (Channel 2).
Figure 6 is the switching waveform of a half bridge;
This half-bridge consists of two GaN devices with integrated drivers in an 8mm x 8mm quad flat no-lead (QFN) package. Channel 2 shows the SW node, where the high-level device is hard-switched at a slew rate of 120V/ns with a bus voltage of 480V. This optimized driver integrated package and PCB limit overshoot to less than 50V. One thing to note is that a 1GHz oscilloscope and probe were used to capture the waveforms.
Package integration of GaN transistors with their drivers eliminates common source inductance, enabling high current slew rates. It also reduces gate loop inductance to minimize gate stress during turn-off and improves device turn-off retention. Integration also enables designers to build efficient thermal and current protection circuits for GaN FETs.
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