“In highly reliable and high-performance applications, such as electric/hybrid vehicles, isolation barrier drivers need to ensure that the isolation barrier is intact under all conditions. With the continuous improvement of Si-MOSFET/IGBT and the introduction of GaN and SiC process technology, the power density of modern power converters/inverters continues to increase. Therefore, there is a need for a new, highly integrated and durable isolated gate driver. The electrical isolation device of these drivers is small and can be integrated on the driver chip. This electrical isolation can be achieved by integrating high-Voltage micro-transformers or capacitors. 1, 2, 3 An unexpected system failure can cause the power switch or even the entire
“
This article deliberately damages the IGBT/MOSFET power switch to study the withstand performance of the gate driver isolation barrier.
In highly reliable and high-performance applications, such as electric/hybrid vehicles, isolation barrier drivers need to ensure that the isolation barrier is intact under all conditions. With the continuous improvement of Si-MOSFET/IGBT and the introduction of GaN and SiC process technology, the power density of modern power converters/inverters continues to increase. Therefore, there is a need for a new, highly integrated and durable isolated gate driver. The electrical isolation device of these drivers is small and can be integrated on the driver chip. This electrical isolation can be achieved by integrating high-voltage micro-transformers or capacitors. 1, 2, 3 An unexpected system failure can cause damage and explosion of the power switch or even the entire power Inverter. Therefore, it is necessary to study how to safely implement the isolation function of the gate driver for high power density inverters. Must test and verify the reliability of the isolation barrier in the worst case (power switch is destroyed).
Introduction
In the worst case, that is, when the high-power MOSFET/IGBT fails, the inverter capacitor bank of several thousand µF will quickly discharge. The released current can cause damage to the MOSFET/IGBT, explosion of the package, and discharge of plasma into the environment. 4 Part of the current entering the gate drive circuit will cause electrical overload. 5 Due to the extremely high power density, when making the driver chip, it is necessary to ensure that even if the chip itself fails, it can still maintain electrical isolation.
Construction of highly integrated modern gate driver
Chip-level isolation uses a Planar micro-transformer method to provide electrical isolation. It is manufactured using wafer-level technology and configured to the size of a semiconductor device. 1iCoupler® channel contains two integrated circuits (ICs) and multiple chip-scale transformers (Figure 1). The isolation layer provides an isolation barrier that separates the top and bottom coils of each transformer (Figure 2). The digital isolator uses a polyimide insulating layer with a thickness of at least 20 μm, which is placed between the planar transformer coils during the wafer manufacturing process. This manufacturing process integrates isolation components with any wafer semiconductor process at low cost to achieve excellent quality and reliability. The cross-sectional view of Figure 2 shows the number of turns of the top and bottom coils separated by a thicker polyimide layer.
Figure 1. The chip configuration of the ADuM3223 MOSFET half-bridge driver.
The tap lead frame in the package completes the isolation. When the gate driver output chip is damaged by the explosion of the power switch, the internal chip partition and configuration must ensure that the isolation layer is intact. In order to ensure that the gate driver is not damaged, the following protective measures have been taken:
► Reasonably set the size of the external circuit to limit the current flowing to the gate driver chip
► Reasonably configure output transistors on the driver chip
► Reasonably configure micro-transformers on the chip
► Reasonably arrange and control the driver chip in the package
Figure 2. ADuM3223: Cross section of microtransformer.
The internal chip configuration of the ADuM3223 gate driver (Figure 1) shows an example of a chip configuration that can avoid electrical isolation faults during extreme electrical overloads.
Destructive testing that simulates the worst inverter fault conditions
Construct a 385 V and 750 V two-level voltage test circuit to simulate the real power inverter situation. In systems that use 110 V/230 V ac power grids and need to implement power factor correction, 385 V voltage levels are extremely common. In drive applications using switches with a rated breakdown voltage of 1200 V, the 750 V voltage level is extremely common for the high-power inverters used.
In a destructive test, the inverter bridge arm consisting of a power switch and an appropriate driver is turned on until the switch fails. The waveform during the destruction process will be recorded to determine the level that flows into the gate driver chip. Several protective measures have been tested to limit the breakdown current flowing into the gate driver circuit. Various IGBTs and MOSFETs are used in destructive tests.
Test circuit to control the damage degree of MOSFET/IGBT
In order to implement the IGBT/MOSFET driver electrical overload test (EOS test), a circuit very close to the real situation was constructed. The circuit contains capacitors and resistors suitable for inverters in the power range of 5 kW to 20 kW. The axial gate resistor Rg uses a metal resistor with a rated power of 2 W. In order to prevent the current from entering the external power supply from the high-voltage circuit in the reverse direction, a blocking diode D1 is used. This also reflects the real situation, because the floating power supply includes at least one rectifier (ie bootstrap circuit). The high-voltage power supply (HV) charges the electrolytic capacitor block through a circuit including a charging resistor Rch and a switch S1.
When implementing the EOS test, a 500µs turn-on signal is used to control the input VIA or VIB. The turn-on signal is transmitted through micro-isolation, which will cause a short circuit and damage the power transistor T1. In some cases, the transistor package explodes.
A total of four power switches (two-level voltage) are used to simulate the damage of the inverter. The first tests implemented for a specific switch type were carried out successively without and with the use of power limiting circuits. In order to limit the current flowing into the driver circuit during the damage phase, some tests directly configure the Zener diode Dz (BZ16, 1.3 W) at the output pin of the driver. In addition, various gate resistance values have also been studied.
Figure 3. The EOS circuit layout of the ADuM4223 used to measure the impact of power switch damage on isolation withstand performance.
Figure 4. The EOS circuit layout of the ADuM4223 used to determine the isolation withstand power limit.
Figure 5. The EOS circuit of the ADuM4223 in the worst case (when the input and output chips are directly exposed to current).
Test circuit for direct damage to gate drive circuit without power limitation
Another experiment was conducted to simulate the worst-case scenario, in which the input and output chips of the gate driver were directly exposed to the breakdown current (destructive energy). In this destructive test, a fully charged large-capacity capacitor was directly connected to the output pin of the gate driver (Figure 4). The test shows the most serious overload situation that may occur, thereby testing the tolerance of its isolation function. The current flows directly into the drive circuit, and the gate resistor is the only power limiting device. Relay S2 couples the high voltage to the gate driver output circuit.
Figure 5 shows the worst-case test, where no device is used to limit the current flowing into the input and output chips. The 750 V high voltage is directly applied to the output chip through the switch S1, that is, in the case of no current-limiting gate resistor, the medium and high voltage 750 V is directly applied to the driver chip in the worst case.
Another possible worst-case scenario is that an excessively high power supply voltage is applied to the main-side control chip of the driver. The recommended maximum input power supply voltage is 5.5 V. If the DC-DC converter that generates the input voltage loses its regulating ability, its output voltage will increase. When the regulation is lost, the output voltage of the converter can be increased to 2 to 3 times that of the first-class DC-DC converter. The ADuM4223 input chip can withstand limited power, and other devices such as resistors, power switches, inductors, etc. are in their respective positions as usual. These devices will hinder the flow of current into the control chip. In order to truly simulate the failure of the DC-DC converter, a power supply voltage with a current limit of 15 V and 1.5 A is selected.
Experimental result
Table 1 shows the results of the overload test using the circuits in Figure 3, Figure 4, and Figure 5. In order to determine the role of the protection circuit, two tests were carried out for each MOSFET/IGBT power switch type. In the worst-case tests of 9, 10, and 11, mechanical switches S1 and S2 were used.
Table 1. Destructive tests under different power switches and different damage conditions
|
test |
ADuM4223 |
PhD# |
U/V |
Rg |
Dz |
result |
Ed/mJ |
Annotation |
switch |
Circuit |
|
1 |
1 |
B |
385 |
4.7 |
not yet |
damage |
8.5 |
FDP5N50 |
image 3 |
|
|
2 |
1 |
A |
385 |
2 × 2.2 |
16 |
Undamaged |
3.5 |
FDP5N50 |
image 3 |
|
|
3 |
2 |
A |
385 |
2 × 2.2 |
16 |
damage |
Rg, DZ no problem |
2xFDP5N50 |
image 3 |
|
|
4 |
2 |
B |
385 |
12 |
16 |
Undamaged |
2xFDP5N50 |
image 3 |
||
|
5 |
2 |
B |
385 |
4.7 |
16 |
Undamaged |
0.5 |
spw24N60C3 |
image 3 |
|
|
6 |
2 |
B |
385 |
3.9 |
not yet |
Undamaged |
spw24N60C3 |
image 3 |
||
|
7 |
2 |
B |
750 |
4.7 |
16 |
Undamaged |
20 |
Rg is damaged, DZ is no problem |
ixgp20n100 |
image 3 |
|
8 |
2 |
B |
750 |
4.7 |
not yet |
damage |
25 |
Rg damage |
ixgp20n100 |
image 3 |
|
9 |
1 |
A |
150 |
4.7 |
not yet |
damage |
Rg damage |
Switch S2 |
Figure 4 |
|
|
10 |
3 |
A |
750 |
0 |
not yet |
damage |
Worst-case output chip |
Switch S1 |
Figure 5 |
|
|
11 |
4 |
enter |
15 |
0 |
not yet |
damage |
Worst-case input chip |
Switch S2 |
Figure 5 |
Figure 6. Waveform diagram generated by damaged SPW2460C3; no damage to the drive was found.
Figure 7. Waveform diagram generated by damaged 2xFDP5N50 (parallel); the gate driver has failed.
In general, Zener diodes can help protect the drive circuit, as shown in the table (Comparison Test 1 and Test 2). But when the value of the gate resistance is too small, even though the Zener diode is used, the driver will still be damaged (compare test 3 and test 4).
By comparing Test 2 and Test 3, and Test 3 and Test 4, the current that damages the drive can be estimated. A very interesting conclusion can be drawn from experiments 5 and 6: Compared with IGBTs of the same power level, super-junction MOSFETs seem to significantly reduce the power level flowing into the gate driver. The purpose of experiments 9, 10 and 11 (without limiting the current flowing into the control and driver chips) is to study the worst-case isolation barrier tolerance.
Different destruction performance of MOSFET and IGBT
The destructive test showed various waveforms when the power switch was damaged. Figure 6 shows the waveform of a super junction MOSFET. The time interval between turning on the circuit and chip damage is about 100µs. Only a very limited amount of current flows into the driver chip, which is subject to overload conditions. Under the same test conditions, the gate current and overvoltage generated by the standard MOSFET are significantly higher, causing damage to the driver, as shown in Figure 7.
Chip damage analysis
Some gate driver packages have similar chip damage for different switches and different test conditions. Figure 8 shows the damage of the P-MOSFET output driver stage in Experiment 8 (Table 1). When the body voltage was 750 V, the test caused the IGBT to explode and the current-limiting devices Rg and DZ were damaged; however, only a small area of melting near the wire bonding position of the pin VDDA could be seen. In the damage stage, the gate overcurrent flows into the 100 µF capacitor through the built-in P-MOSFET diode. The area near the wire welding melted due to overcurrent. There was no further damage to the driver chip, and no further isolation damage to the control chip. Figure 9 shows the melting area during Experiment 9, in which a high voltage of 150 V was directly applied to the driver chip. The electrical isolation of the control chip passed this extreme overload test.
Figure 8. Photo of the gate driver chip, showing the location of the damage during trial 8 (ADuM4223 #1). Only a small piece of the output chip surface is burned out. No damage to the isolation barrier was found.
Figure 9. Photograph of the gate driver chip, showing the location of the damage during experiment 9 (ADuM4223 #2). Extreme electrical overload failed to damage the control chip. No damage to the isolation barrier was found.
Figure 10. Photograph of the gate driver chip, showing the location of the damage during test 10. The output driver applied ultra-high power and damaged the circuit; burned out in a large area. However, the isolation barrier was not damaged.
The worst case on the main side shows the application of ultra-high power supply voltage to the control chip. Therefore, in Experiment 11, a 15 V power supply voltage was applied to the VDD1 pin (Figure 5), which clearly exceeded the 7.0 V absolute maximum rating. The photo in Figure 11 shows a part of the chip near the VDD1 pin is burned out.
Figure 11. A photo of the input control chip, showing the location of the damage during test 11. The current applied to the circuit is at VDD1A small area of damage was caused around the pins. No damage to the isolation barrier was found.
in conclusion
Destructive testing of power switches will not affect the isolation barrier tolerance of the integrated gate driver ADuM4223/ADuM3223. Even if the driver is damaged due to excessive current flowing into the output chip, it is only partially burnt out in a small area. The excess current flows into the DC blocking capacitor through the P-MOS drive transistor. Therefore, only the P-MOS area melts.
The chip configuration of the ADuM4223/ADuM3223 does not allow the molten area to spread to the control chip, which includes the electrical isolation signal transformer. In order to limit the current flowing into the output of the driver, a Zener diode can be used. The Zener diode is used in combination with an appropriate gate resistance to protect the gate driver when the power switch is damaged. It can be designed to use gate resistors to manage power consumption during normal operation and isolate the driver from the power switch when it is damaged. When high voltage is directly applied to the chip, the gate resistor acts as a fuse. The resistance will control the degree of chip damage and control it within a small range around the output power switch.
In the worst case, when high power is applied to the output chip, a small area of damage will occur near the output pins of the driver. This test will not affect the withstand performance of the isolation. In the worst-case scenario on the main side, when the power supply voltage is significantly higher than the absolute maximum rating, a small area of damage will occur around the power supply voltage pin. In all electrical overload tests, there was no sign of weakening of the isolation function. The subsequent high-voltage isolation test verified the withstand performance of the electrical micro-isolation. Proper chip structure and chip configuration inside the driver package can prevent the breakdown voltage from spreading to the high-voltage isolation layer of the micro-transformer.
references
1 Baoxing Chen, Bernhard Strzalkowski. “Isolated gate driver with microtransformer.” ECPE workshop “Electronic components around the power switch.” June 29, 2011.
2 Andreas Volke, Michael Hornkamp, Bernhard Strzalkowski. “Application of IGBT/MOSFET based on coreless transformer driver IC 2ED020I12-F.” Proceedings of PCIM 2004, Nuremberg, 2004.
3 SLLA198, “ISO72x series of high-speed digital isolators.” Texas Instruments.
4 Bernhard Strzalkowski. “High-performance IGBT drivers using micro-transformer technology provide excellent isolation performance.” Proceedings of PCIM2007, Nuremberg, 2007.
5 Bernhard Strzalkowski. “The maximum power limit for IGBT/MOSFET gate drivers to provide isolation.” Proceedings of PCIM 2014, 2014.
About the Author
Bernhard Strzalkowski studied electrical engineering at Silesian University of Technology in Gliwice, Poland and Karlsruhe University of Technology in Germany, and obtained a master’s degree in electrical engineering from Karlsruhe University in Germany in 1989. In 2003, he received a doctorate degree in electronics from Silesian University of Technology. From 1989 to 1996, he worked as a magneto R&D engineer in Starnberg, responsible for the development of power electronics for wind power converters and electric/hybrid vehicles. From 1997 to 2008, he joined Siemens/Infineon in Munich, where his research and design work included integrated circuits for industrial/automotive applications. He joined ADI in Munich, Germany in February 2009 and is responsible for power management, digital power and iCoupler digital power and iCoupler applications. He provides support to European automotive/communication infrastructure customers and has obtained a number of patents related to the field of power electronics. He is a member of the ICE and VDE standards committees and the PCIM advisory committee. Contact information:[email protected]
