In the engineering world, decisions often come from deep analysis. Simple decisions can require days, weeks, or even months of careful research. Ask your engineer friend how much time he or she spends deciding which camera or laptop to buy, most likely he or she spends researching product specs, reading product reviews, and buying products in stores More time than all your other friends combined. Surprisingly, this attention to detail isn’t limited to engineering work itself, such as the QA story of a new signoff timing tool. Let’s explore the reasons for this phenomenon and describe the steps engineers should take to verify the quality of new tools.
In an ideal world, designers would always have the time and expertise to run SPICE-level associations, but in reality there isn’t enough time or expertise. The product development cycle is always short, which makes designers spend most of their time on product development, and SPICE technology, fresh from school, has gradually deteriorated after years of digital design. Relying on their familiarity, designers can use their existing static timing analysis tools (STA) as a reference for quality verification of new tools.
For more than 15 years, the timing signoff world has been dominated by Synopsys’ PrimeTime (PT); countless designers have successfully tapped this tool, and the available silicon produced by this tool has also immeasurable. In a sense, PrimeTime has become a representation of SPICE as the gold standard for timing. At 28nm and below, this is not a safe and reasonable assumption to make, and many engineers are looking for alternatives.
The pitfalls of next-generation STA tools versus PrimeTime
Unfortunately, the evaluation process for the new timing signoff tool is not complete. In most cases, engineers are only interested in comparing newer tools to PT, with little regard for their SPICE correlation. The specific reasons are as follows:
1. The engineer may not have the expertise to conduct SPICE correlation;
2. Engineers really don’t have time for SPICE-level correlation;
3. The design has been successfully cast with PT for many years, so the new tool needs to be “good enough” with a high level of comfort compared to PT.
Without the SPICE connection, engineers have no way of knowing how their designs work in the chip. They can only assume that the availability of a chip means that their STA tool is accurate, but in fact there are several factors that can mask the poor accuracy while still producing a usable chip. Dynamic Voltage drop tolerance, synchronous switching output noise (SSO), on-chip variation (OCV) over temperature/voltage and process, and pessimistic tendencies for corner extraction can all form a large safety net that completely obscure the inconsistencies of the tool. precision. This is especially true if the chip is fabricated in the middle of the process window. Ensuring SPICE correlation results in tighter margins, less overdesign, and better power consumption.
Linking to other sequencers is bound to cause many problems, making it difficult to meet requirements. The most obvious impediments are the lack of a neutral gold reference and the ever-changing baseline reference presented by PT. In recent years, “accuracy” has been giving way to “run time”, and in the end it has been sacrificed to improve run time at the expense of increased conservatism. But even if today’s de facto standard doesn’t change from quarter to quarter, temporal correlation will still be a very difficult task. Since most current sequencers are based on asymptotic waveform evaluation (AWE), they all have their own secret sauce for modeling crosstalk delays. This also makes it problematic to escort the gold reference to its secret weapon. Also, for more precise associations, designers must run these tools in exactly the same way. These associated variables can be divided into two types:
Control settings are numerous and varied, including interference source filtering for crosstalk delay calculations. In this area, there are several variables that must be set equally, including the coupling and capacitive interferer ratio, Vdd bump height percentage, and interferer window filtering. Additionally, key net reselection criteria are key to properly comparing one sequencer to another. It is well known that all sequencers are “conservative by birth” at the first timing window fusion iteration. This leads to increased matching difficulty for paths without timing problems, since they are computed using conservative heuristics. Slight inaccuracy will not cause path failure, but will have a significant impact on runtime.
Even though each tool uses its most precise algorithm, the tool itself remains irrelevant based on the calculation principle of the noise impact induced by the interference source. Another example of introducing errors is managing delay calculations when the victim network crosses the switch threshold more than once in a single transmission. Here’s the point: Unless all EDA vendors come together and agree to adopt crosstalk modeling algorithms as standard, these tools will never be fully correlated. (Using SPICE as a golden reference? Maybe. Oh wait, that’s too much work!)
Tekton, Magma’s next-generation static timing analysis tool, offers overwhelming performance advantages over PrimeTime and Cadence ETS, while also working to correlate with legacy SPICE-like reference tools. PrimeTime’s inherent SPICE correlation uncertainty and up to 5x faster Tekton runtimes have greatly lowered the threshold of “what is an acceptable correlation for PrimeTime”, as long as you can account for outliers.
Sign-off quality inspection
What does an engineer do to verify the quality of a new tool, such as Tekton’s “signoff” accuracy? History and experience tell us that the correlation between STA tools will be no better than a path delay of 2-3%. why? Because most, if not all, vendors state that their tool accuracy is 2-3% SPICE. SPICE is prepared to be available in some form to each vendor, and vendors can fine-tune their tools to match SPICE requirements. If 2-3% SPICE is the best value achievable under ideal conditions, how much better can one vendor’s tool be compared to another vendor’s tool when there are no shared parts? Not much better. Statistically, the correlation would be much better if you had seen the mean and standard deviation values. This is because the analysis of outliers outside the statistical range can be done by using SPICE-level analysis techniques. What can be proven in these cases is that even PrimeTime has been wrong on many occasions.
Sign-off quality inspections then become more compliant with a single set of associated criteria. The first step is to achieve a reasonable statistical correlation goal; by a reasonable goal is meant that it will be within the same error range (SPICE-related) that the current signoff tool states. For the reasons already discussed above, this can be far more achievable than setting an absolute accuracy target. For example, trying to obtain 50ps timing correlation of existing signoff tools when current tool accuracy is only within 75ps SPICE is futile. The second step is to look at the outliers related to SPICE. EDA vendors need to make this easier for design engineers. SPICE correlation with on-path crosstalk is at least a chore. Once these two steps are achieved, most engineers will have the confidence to use the new tool in production for every part of the timing flow except the final timing run. The first choice for testing chips with new technology is a single sign-off tool because risk can be mitigated by running the chip within the enterprise and controlling voltage and temperature. Chip success is the last step in final signoff quality inspection and adoption.
As the industry’s latest generation of STA tools, Tekton will attract new contracts from today’s leading integrated device manufacturers (IDMs), fabless semiconductor companies and foundries. With this new contract, which tends to be compared to SPICE-based reference standards, these companies will be confident that they will be able to fully adopt and take advantage of Tekton’s superior technology, including high-performance multi-threading, concurrent multi-mode multi-angle analysis, and a host of other capabilities.
Author: Ruben Molina
Director of Magma Design and Implementation Business Department
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