Advances in semiconductor technology have driven the popularity of phased array antennas across the industry. The transition from mechanically steered antennas to Active Electronically Scanned Antennas (AESAs) in military applications began a few years ago, but only recently has it seen rapid development in satellite communications and 5G communications. Small AESAs offer several advantages, including the ability to turn quickly, generate multiple radiation patterns, and provide greater reliability; however, until major advances in IC technology, these antennas will not be widely available. Planar phased arrays require highly integrated, low-power, high-efficiency devices that allow users to install these components behind the antenna array while maintaining acceptable levels of heat generation. This article will briefly describe how the development of phased array chipsets is driving the realization of planar phased array antennas, with examples to aid in the explanation and illustration.
Over the past few years, we have used parabolic dishes extensively to transmit and receive signals where directivity is important. Many of these systems perform well, keeping costs relatively low after years of optimization. But these mechanically steered dishes have some drawbacks. They are bulky, slow to operate, have poor long-term reliability, and can only provide one desired radiation pattern or data stream.
Phased array antennas use an electrical signal steering mechanism, which has many advantages, such as low height, small size, better long-term reliability, fast steering, multi-beam, etc. A key aspect of phased array antenna design is the spacing of the antenna elements. Most arrays require element spacing of about half a wavelength, thus requiring more complex designs at higher frequencies, driving ICs at higher frequencies to achieve higher levels of integration and more advanced packaging solutions.
There has been considerable interest in applying phased array antenna technology to a variety of applications. However, limited by the ICs currently available, engineers have been unable to make phased array antennas a reality. Recently developed IC chipsets successfully solve this problem. Semiconductor technology is moving toward advanced silicon ICs, which allow us to combine digital control, memory, and RF transistors into the same IC. In addition, gallium nitride (GaN) significantly increases the power density of power amplifiers, which can help to drastically reduce the footprint.
Phased Array Technology
ICs have played a major role in the industry’s transition to smaller arrays with reduced volume and weight. The traditional circuit board construction basically uses a small PCB board with the Electronic components fed vertically into the back of the antenna PCB. Over the past 20 years, this method has been refined to continue to reduce the size of the circuit board and thus the depth of the antenna. Next-generation designs move from this board structure to a flat-panel approach, which greatly reduces the depth of the antennas, making them easier to fit into portable or airborne applications. Achieving the smaller size requires a sufficient level of integration of each IC to fit them into the back of the antenna.
In a planar array design, the space available for the IC on the back of the antenna is limited by the spacing of the antenna elements. For example, at scan angles up to 60°, a maximum antenna element spacing of 0.54 λ is required to prevent grating lobes. Figure 1 shows the maximum element spacing (in inches) versus frequency. As frequencies increase, the spacing between elements becomes very small, thereby crowding out the space required for components behind the antenna.
Semiconductor Technology and Packaging
Microwave and millimeter-wave (mmW) IC components that are the building blocks of phased array antennas are shown in Figure 3. In the beamforming section, attenuators adjust the power level of each antenna element to reduce grating lobes in the antenna pattern. Phase shifters adjust the phase of each antenna element to steer the antenna main beam, and switches are used to switch between transmitter and receiver paths. In the front-end IC section, a power amplifier is used to transmit the signal, a low-noise amplifier is used to receive the signal, and finally, another switch is used to switch between the transmitter and receiver. In past configurations, each IC was offered as a separate packaged device. More advanced solutions use an integrated monolithic single-channel gallium arsenide (GaAs) IC to accomplish this. For most arrays, the beamformer is preceded by a passive RF combiner network, receiver/exciter, and signal processor, which is not shown in the figure.
The popularity of phased array antenna technology in recent years is inseparable from the promotion of the development of semiconductor technology. Advanced nodes in SiGe BiCMOS, silicon-on-insulator (SOI), and bulk CMOS merge digital and RF circuits together. These ICs can perform digital tasks in the array, as well as control the RF signal path to achieve the desired phase and amplitude adjustments. Today, we can implement multi-channel beamforming ICs that adjust gain and phase in a 4-channel configuration, supporting up to 32 channels, for mmWave designs. In some low-power examples, silicon-based ICs have the potential to provide single-chip solutions for all of the above functions. In high-power applications, GaN-based power amplifiers significantly increase power density and can be incorporated into the element building blocks of phased array antennas. These amplifiers have traditionally used traveling wave tube (TWT) based technology or relatively low power GaAs based ICs.
In airborne applications, we are seeing an increasing trend for flat panel architectures, which also offer the power-added efficiency (PAE) benefits of GaN technology. GaN also enables large ground-based radars to move from TWT-powered dishes to phased-array-based antenna technologies powered by solid-state GaN ICs. We currently have access to single-chip GaN ICs that deliver over 100 W of power with a PAE of over 50%. Combining this level of efficiency with the low duty cycle for radar applications enables a surface mount solution to dissipate the heat generated in the housing base. These surface mount power amplifiers greatly reduce the size, weight and cost of antenna arrays. Beyond the pure power capabilities of GaN, an additional benefit over existing GaAs IC solutions is the reduced size. For example, 6 W to 8 W GaN-based power amplifiers in the X-band can reduce the footprint by 50% or more compared to GaAs-based amplifiers. This reduction in footprint has significant implications when assembling these electronics into the element components of a phased array antenna.
The development of packaging technology has also greatly reduced the cost of planar antenna architectures. A high-reliability design may use a gold-plated hermetic enclosure with chips and cables interconnected inside. These enclosures are more robust in extreme environments, but are bulky and expensive. A multi-chip module (MCM) integrates multiple MMIC devices and passive components into a relatively low-cost surface-mount package. MCMs still allow for a mix of semiconductor technologies in order to maximize the performance of each device while saving significant space. For example, front-end ICs may contain PAs, LNAs, and T/R switches. Thermal vias or solid copper scrap in the package base are used for heat dissipation. To save costs, many commercial, military and aerospace applications are beginning to use lower cost surface mount packaging options.
Phased Array Beamforming ICs
Integrated analog beamforming ICs, commonly referred to as core chips, are designed to support a wide range of applications including radar, satellite communications, and 5G communications. The main function of these chips is to accurately set the relative gain and phase of each channel to increase the signal in the desired direction of the main beam of the antenna. This beamforming IC was developed for analog phased array applications or hybrid array architectures that combine some digital beamforming techniques with analog beamforming techniques.
The ADAR1000 X-/Ku-band beamforming IC is a 4-channel device covering the frequency band from 8 GHz to 16 GHz in time division duplex (TDD) mode with the transmitter and receiver integrated into a single IC. In receive mode, the input signal is passed through four receive channels and combined in the general purpose RF_IO pin. In transmit mode, the RF_IO input signal is split and passed through four transmit channels. The functional block diagram is shown in Figure 4.
A simple 4-wire serial port interface (SPI) controls all on-chip registers. Two address pins allow SPI control of up to four devices on the same serial cable. Dedicated transmit and receive pins synchronize all core chips in the same array, and a single pin controls fast switching between transmit and receive modes. This 4-channel IC is housed in a 7 mm x 7 mm QFN surface mount package for easy integration into flat panel arrays. The high level of integration, coupled with a small package, can solve some of the size, weight and power challenges in phased array architectures with high channel counts. The device consumes only 240 mW/channel in transmit mode and 160 mW/channel in receive mode.
The transmit and receive channels are directly available and can be used with front-end ICs in external designs. Figure 5 shows the gain and phase plots of the device. With full 360° phase coverage, phase steps of less than 2.8° and gain adjustment better than 30 dB can be achieved. The ADAR1000 integrates on-chip memory that can store up to 121 beam states, one of which contains all phase and gain settings for the entire IC. The transmitter provides about 19 dB of gain and 15 dBm of saturation power, with a receive gain of about 14 dB. Another key metric is the phase change within the gain setting, which is about 3° over a 20 dB range. Again, the gain variation in phase is about 0.25 dB over the entire 360° phase coverage, easing calibration challenges.
The ADTR1107 CPLR_OUT coupler output can be connected back to one of the four ADAR1000 RF detector inputs (DET1 to DET4 in Figure 4) to measure transmit output power. These diode-based RF detectors have an input range of −20 dBm to +10 dBm. The coupling coefficient of the ADTR1107 directional coupler ranges from 28 dB at 6 GHz to 18 dB at 18 GHz.
The ADTR1107 can be pulsed with the gate Voltage driven by the ADAR1000 while keeping the drain constant. This method is more optimal than pulsing through the drain because it uses high power MOSFET switches and gate driver devices and gate switches, the latter using low current. It should also be noted that sufficient power from the ADAR1000 in transmit mode will saturate the ADTR1107 and the ADTR1107 can withstand the total reflected power when the antenna is shorted.
The combined performance of the ADTR1107 and ADAR1000 in the 8 GHz to 16 GHz frequency range in transmit and receive modes is shown in Figure 9. In transmit mode, they provide about 40 dB gain and 26 dBm saturation power, and in receive mode, they provide about 2.9 dB noise figure and 25 dB gain.
Figure 10 shows 4 ADAR1000 chips driving 16 ADTR1107 chips. Simple 4-wire SPI controls all on-chip registers. Two address pins allow SPI control of up to four ADAR1000 chips on the same serial cable. Dedicated transmit and receive load pins also synchronize all core chips in the same array, and a single pin controls fast switching between transmit and receive modes.
Transceiver Chipsets and Other Companion Products
Highly integrated RF transceiver chips can improve integration at the antenna level. The ADRV9009 is a good example of such a chip. It offers dual transmitters and receivers, an integrated frequency synthesizer and digital signal processing. The device features an advanced direct conversion receiver with high dynamic range, wide bandwidth, error calibration and digital filtering. A variety of auxiliary functions are also integrated, such as analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), as well as general-purpose input/output and RF front-end control for power amplifiers. A high-performance phase-locked loop provides fractional-N RF frequency synthesis for both the transmitter and receiver signal paths. It offers extremely low power consumption and comprehensive shutdown modes to further conserve power when not in use. The ADRV9009 is available in a 12 mm × 12 mm, 196-pin chip-scale ball grid array package.
Analog Devices provides the entire signal chain from the antenna in place for phased array antenna designs and optimizes ICs for this application to help customers speed time to market. Advances in IC technology have prompted a shift in antenna technology, driving change across multiple industries.
About the Author
Jeff Lane, a graduate of MIT with a master’s degree in electrical engineering, joined ADI in 2001. He has experience in microwave antenna design, systems engineering, sales and marketing. He is currently a product marketing engineer in the Aerospace, Defense and RF Products Group at Analog Devices, where he focuses on RF and microwave MMIC amplifiers.