“Mounting ESD protection elements such as multilayer chip varistors and Zener diodes near the source of ESD can effectively deal with ESD. However, the intrusion path of ESD is difficult to determine, which often leads to the situation that the installed ESD protection element does not exert its original strength. In order to exert the original strength of the component, we must determine the intrusion path of ESD, and it needs to be installed near the source of ESD. That’s why we’ve investigated the importance of mounting locations using an ESD visualization system, which we’ll walk you through in this tweet.
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Mounting ESD protection elements such as multilayer chip varistors and Zener diodes near the source of ESD can effectively deal with ESD. However, the intrusion path of ESD is difficult to determine, which often leads to the situation that the installed ESD protection element does not exert its original strength. In order to exert the original strength of the component, we must determine the intrusion path of ESD, and it needs to be installed near the source of ESD. That’s why we’ve investigated the importance of mounting locations using an ESD visualization system, which we’ll walk you through in this tweet.
Introduction video
ESD Visualizer – Optimized Substrate Layout
An ESD visualization device is a device that visualizes ESD current by automatically scanning ESD current with a non-contact magnetic field probe. Because the electric field intensity distribution in the scanning area can be obtained, it is an effective tool for optimizing the substrate layout in ESD protection countermeasures. With this device, it is possible to observe the movement of ESD on the substrate depending on the mounting position of the ESD protection element.
Figure 1 ESD visualization equipment
ESD response depending on mounting position (Multilayer Chip Varistor)
ESD response was evaluated using the following substrates. The protection target products use LEDs, and the ESD protection elements use multilayer chip varistors. Install chip varistors at about 10mm and about 40mm from the pivot point (★) in the figure below, and observe the movement of each ESD.
Figure 2 Evaluation substrate and verification conditions
ESD trends when chip varistors are mounted at about 10mm (left) and about 40mm (right). The closer the chip varistor is placed, the more ESD flows to the varistor and the less ESD flows to the LED line.
The ESD reaction is as follows:
① Installation position 10mm
② Installation position 40mm
It can be seen that when the installation position of the chip varistor is about 10mm away from the fulcrum, ESD will flow into the installation line of the varistor immediately after entering the circuit. Even at the peak time of ESD, it can be seen that it mainly flows to the chip. Varistor installation wiring.
Figure 3 Time delay before and after ESD application (installation position: 10mm)
On the other hand, when the mounting position of the chip varistor is about 40mm away from the fulcrum, ESD flows into the LED line immediately after entering the circuit, and also flows into the LED line at the peak. This means that a relatively high electrical load is applied to the LEDs.
Figure 4 Time delay before and after ESD application (installation position: 40mm)
Optimum Mounting Configuration of Chip Varistors in ESD Countermeasures
Field strength analysis of the mounting location of the chip varistor shows that ESD is introduced about 0.3ns faster at 10mm (blue). This 0.3ns time is a very significant difference for an ESD with a peak time of about 1ns. In addition, the electric field strength at the peak is higher because the ESD can be introduced earlier. This means that more ESD can be introduced onto the chip varistor if the chip varistor is mounted close to the source of ESD entry.
Figure 5 Electric field strength
Under the above verification conditions, the ESD withstand Voltage was actually measured, and it was found that the ESD withstand voltage was higher when the ESD protection components were installed and the installation position was closer to the ESD entry source. This means that in order to take better ESD countermeasures, it is most appropriate to mount the chip varistor close to the source of ESD entry.
Figure 6 ESD withstand voltage
TDK’s Chip Varistors for Optimal ESD Countermeasures and Optimal Substrate Layout
With the complexity of substrates, even if the source of ESD intrusion can be identified, it can be limited by the nearby installation space. One of the features of TDK’s multilayer chip varistors is the inclusion of a miniaturized product lineup. The chip varistor we are currently mass-producing has a minimum size of EIA01005 (0.4 x 0.2 mm) for consumer products, and the industry’s smallest EIA0402 (1.0 x 0.5 mm) for automotive. Therefore, if TDK chip varistors are used, space can be saved, and installation and deployment with a high degree of freedom can be realized.
Figure 7 Features of TDK’s special chip varistors: miniaturization
The Links: ACM1602B G270QAN010
