EV12AQ605, the optimized version of EV12AQ600 for highly competitive high-volume applications

“Teledyne e2v has developed a new version of the latest 12-bit quad-core high-speed large-bandwidth ADC. The pins of EV12AQ605 and EV12AQ600 are fully compatible. This new ADC version is mainly for the commercial and industrial market sectors with high volume.

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Teledyne e2v has developed a new version of the latest 12-bit quad-core high-speed large-bandwidth ADC. The pins of EV12AQ605 and EV12AQ600 are fully compatible. This new ADC version is mainly for the commercial and industrial market sectors with high volume.

Common pin distribution of EV12AQ600 and EV12AQ605 (top view)

Customers can design systems that run EV12AQ605 independently or synchronously to work in different modes such as four-channel 1.6Gsps, dual-channel 3.2Gsps, or single-channel 6.4Gsps. By using the same ADC model to configure different systems, it can meet the needs of large-volume end applications.

EV12AQ605 includes the proven chain synchronization function, which has been applied in Teledyne e2v’s latest data converter (for more details, please refer to multi-chip ADC synchronization)-synchronization can also be achieved through traditional point-to-point methods. This feature can meet the growing needs of large-scale multi-channel phased array antennas and broadband microwave backhaul multiple-input multiple-output (MIMO) systems, as well as multi-channel digital storage oscilloscopes (DSO), which improves the performance and flexibility of ADCs. Very suitable for communication, test and measurement system applications.

EV12AQ605 configurations with -A- Independent ADC or -B- synchronized ADC

EV12AQ605 is configured as independent working ADC (A) or synchronous working ADC (B)

In addition, EV12AQ605 includes a cross-point switch (CPS), which enables the four cores inside the device to work independently or in pairs at the same time to achieve a sampling rate of 6.4Gsps and the number of channels required by the user.

The following block diagrams show the configuration of 4 channels/2 channels/1 channel available to the ADC, as well as the connection of the input signal to each core and the configuration of the internal clock signal:

EV12AQ605 four-channel mode configuration (sampling rate up to 1.6Gsps per channel)

EV12AQ605 two-channel mode configuration (sampling rate up to 3.2Gsps per channel)

EV12AQ605 single channel mode configuration (sampling rate up to 6.4Gsps per channel)

These features allow system designers to develop devices with high flexibility and scalability.

This ADC fills the gap between the analog radio frequency domain and the digital domain, with an input bandwidth of more than 6.5GHz (extended bandwidth mode):

EV12AQ605 is a specially customized device for customers looking for an optimal cost solution. Customers who have used EV12AQ600 to develop a prototype of the principle can directly switch to EV12AQ605.

The main differences between EV12AQ600 and EV12AQ605 are shown in the table below. All other functions are the same.

Taking into account the calibration required for interleaving mismatch, the chip comes with two sets of calibration values ​​for offset, gain and phase delay, which correspond to low-frequency (below 800MHz) and high-frequency (above 800MHz) applications. Since the calibration value is measured at a fixed temperature in the industrial test process, the interpolation of offset, gain, and phase delay between temperature values ​​is not available. Users can optimize the matching degree of offset, gain and phase by adjusting the values ​​in the corresponding internal registers.