“With the continuous development of integrated circuit technology, high-performance operational amplifiers are widely used in high-speed analog-to-digital converters (ADCs), digital-to-analog converters (DACs), switched capacitor filters, bandgap Voltage references and precision comparators, etc. In various circuit systems, it has become the core unit circuit of analog integrated circuit and mixed-signal integrated circuit design, and its performance directly affects the overall performance of the circuit and system. The design of high-performance operational amplifiers has always been one of the hot spots in the design of analog integrated circuits. A compromise to meet the needs of various application areas.
With the continuous development of integrated circuit technology, high-performance operational amplifiers are widely used in high-speed analog-to-digital converters (ADCs), digital-to-analog converters (DACs), switched capacitor filters, bandgap voltage references and precision comparators, etc. In various circuit systems, it has become the core unit circuit of analog integrated circuit and mixed-signal integrated circuit design, and its performance directly affects the overall performance of the circuit and system. The design of high-performance operational amplifiers has always been one of the hot spots in the design of analog integrated circuits. A compromise to meet the needs of various application areas.
Many modern integrated CMOS op amps are designed to drive capacitive loads only. With such capacitive only loads, there is no need for a voltage buffer for op amps to achieve low output impedance, so it is possible to design op amps with higher speeds and larger signals than those that need to drive resistive loads Amplitude op amp. These improvements are achieved by having only one high impedance node at the output of an op amp that drives only capacitive loads. These op amps see admittance at other nodes on the order of the transconductance of the MOSFET, so they have low impedance.
With all the relatively low impedance internal nodes, the speed of the op amp is maximized, it should also be mentioned here: these low node impedances cause the voltage signal to drop at all nodes but not the output node, however, the current signal of the various transistors can be very large, for these op amps, it should be seen that the compensation is usually achieved by the load capacitance, so as the load capacitance becomes larger, the op amp generally becomes more stable and slower, one of the most important parameters of these modern transistors is their transconductance value (ie the ratio of output current to input current). For this reason, some designers refer to these modern op amps as transconductance op amps or operational transconductance amplifiers (OTA).
In various OTA structures, the operational amplifier of the folded cascode op amp structure allows the designer to optimize the second-order performance index, which is not possible in the traditional two-pole op amp, especially for the cascode technology. It is useful to increase the gain, increase the PSRR value, and allow self-compensation at the output. This flexibility allows the development of high-performance unbuffered operational amplifiers in CMOS processes, which are now widely used in integrated circuits for radio communications.
The op amp introduced in this paper is a folded cascode op amp using TSMC0.18μmM MixedSignalSALICIDE (1P6M, 1.8V/3.3V) CMOS process, and the DC, AC and transient analysis are carried out on it, and finally the design indicators are carried out. compare.
2 Circuit structure analysis
As shown in Figure 1, the figure is a differential input single-ended output design. His basic idea is to apply cascode MOS transistors to the output differential pair, but the MOS transistors used are the same as those used in the input stage. The types of MOS tubes are opposite. For example, the differential pair MOS tubes composed of M1 and M2 in the figure are N-channel. The cascode MOS transistors composed of M1c and M2c are P-channel MOS transistors, and this opposite type of MOS transistors must be arranged to allow the output of this single-gain stage amplifier to be at the same bias voltage level as the input signal. It should be mentioned that even if a folded cascode amplifier is basically a single gain stage, its gain may be very reasonable, around 700-3000. Such a high gain occurs because the gain is determined by the input transconductance and output impedance, which is very high due to the use of cascode technology.
The differential to single-ended transition shown in the figure is made by M5, M5c, M6, M6c. In a differential output design, these may be replaced by 2 wide cascode current sinks, and a common mode feedback circuit can be added.
Compensation is achieved through the load capacitance CL and achieves dominant pole compensation. In applications with very small load capacitance, it may be necessary to add additional compensation capacitors in parallel with the load to ensure stability. If lead compensation is desired, a resistor can be added in series with CL, when lead compensation is not possible in some applications, such as when the compensation capacitor is mainly provided by the load capacitance, this method is suitable in many cases, and many designs The reader doesn’t seem to realize this (that is, in many cases, a resistor in series with the load capacitor is fine).
The bias current of the input differential pair MOS tube is equal to Ib1/2. The bias current of the P-channel cascode MOS transistor at any one (M1c or M2c) is equal to the drain current of M3 or M4 minus Ib1/2, because (W/L)3=(W/L)4 = (W/L)8b, so this drain current is determined by the ratio of Ib and (W/L)81/(W/L)11, since the bias current of one of the cascode transistors is obtained by subtracting the current, So for it to be established accurately, Ib2 and Ib3 need to be obtained from a single bias network. In addition, any mirror current source that obtains these currents should be composed of MOS transistors formed in parallel with MOS transistors of unit size. This method can eliminate errors caused by second-order effects caused by MOS transistors with different widths.
3 Test Analysis
Vdd=3V, Ib=62.5μA, CL=5pF
The parameters of each MOS tube in Figure 1 are shown in Table 1.
By simulating the op amp shown in Figure 1, the voltage transfer curve, frequency response, small-signal gain, output, and output resistance of the open-loop configuration can be simulated.
It can be seen from Figure 2 that the open-loop output voltage swing ranges from 0.3-2.7V. Finally, the comparison between the simulation results and the design indicators is shown in Table 2.
The op amp explained in this article is a folded cascode op amp with high DC open-loop gain, low input offset voltage, high speed, etc. The BSIM3 (V3.2) model parameters of the TSMC0.18 mixed-signal double-well CMOS process , using HSpiceW-2005.03 and other simulation tools to carry out DC, AC and transient analysis.
The simulation results show that the op amp implemented in this paper has a DC open-loop gain of 73dB. Under the condition of 5pF load capacitance, the op amp’s unity gain frequency is 3MHz, the phase margin is 88°, and the output resistance is 47.8MΩ.
As can be seen, the design is almost satisfactory, and small adjustments can make the amplifier work within the specified range by changing the W/L ratio or DC.
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