Arm released a new server chip and roadmap, further challenge X86

Arm released a new server chip and roadmap, further challenge X86

It is a well-known fact that Arm has huge ambitions in the server market, but this is a wish that will take several years to come true. In the past years, although the Arm camp has undergone many doubts and wrong attempts, as of 2020, no one can deny that the server chips driven by the company’s CPU IP are indeed competitive, and they are actually leading position.

Amazon’s Graviton2-the 64-core Neoverse N1 server chip is the first widely used product in this other library. It will promote the development of the Arm server ecosystem and actively attack the current x86 vendors (such as Intel and AMD) Dominant infrastructure CPU market share.

Although this journey is long, its roots can be traced back to the company’s public roadmap as early as 2018. Fast forward to 2020, and not only do we see products with the first-generation Neoverse N1 infrastructure CPU IP enter the market in a commercial and publicly available form, but we have also seen the company achieve its goal of 30% of its target benefits Increased by 2 times.

Neoverse V1: The new highest performance tier infrastructure CPU

Today, we are ready to move towards the next generation Neoverse platform. Arm not only demonstrated the CPU microarchitecture previously known as Zeus, but also showed a new product category beyond the Neoverse N series: the launch of the new Neoverse V series and Neoverse V1 (Zeus), and the appearance of Neoverse N2 (Perseus) New road map.

The new Neoverse V1 introduces the new V series into Arm’s infrastructure IP product portfolio. Essentially, this represents the company’s efforts to pursue higher absolute performance regardless of cost.

At the beginning of this spring, we introduced the company’s new mobile Cortex-X1 CPU IP, which represents an important business model change for Arm: In the past, Arm only provided a single CPU microarchitecture suitable for everyone. The licensee must Adopt a wider range of design and manufacturing solutions. But now in terms of performance, we have seen the difference in microarchitecture. One IP product now focuses on the pure highest performance (Cortex-X1) regardless of area or power consumption cost; while another design (Cortex-A78 ) Focus on Arm products. The more traditional design concept of maximizing PPA (power, performance, area).

The Zeus microarchitecture in the form of Neoverse V1 is essentially the infrastructure counterpart implemented by Arm in the mobile IP products of Hera Cortex-X1 CPU IP: focusing on maximum performance, while paying less attention to power consumption and area.

This means that V1 has a significantly larger cache, core structure, and uses more area and functions to achieve an unprecedented level of performance.

Compared with the Neoverse N1 we see in the chip today, Arm’s new architecture achieves a breakthrough +50 IPC improvement. The potential for performance improvement here is huge, because this is only an ISO frequency upgrade in the same process, and because V1 has increased the frequency through the improvement of the process node, it is very likely that the actual product based on V1 will also receive additional performance improvements. .

If the conservative clock Graviton2 and its 2.5GHz N1 core are used as a benchmark, the theoretical 3GHz V1 chip will increase the single-thread performance per core by 80%. In terms of single-core performance, such a performance increase will not only greatly exceed any current x86 competitors in the server field, but also be comparable to today’s best high-performance desktop chips from AMD and Intel (though we must remember it will Compete with next-generation Zen3 Milan and Willow Cove Sapphire Rapids products.

Neoverse N2 is Perseus: continue to pay attention to PPA

In addition to the Neoverse V1 platform, we also saw a roadmap insertion that was not available before. The design of Perseus will become Neoverse N2 and will be the successor of N1’s effective product positioning. Compared with N1, this new CPU IP represents a 40% increase in IPC, but still maintains the same design philosophy, which is to maximize performance in the lowest power consumption and smallest area.

When we talk about the microarchitecture generation here, it may be a bit confusing, so I made a chart to illustrate that we can call the generation equivalent between Arm’s mobile device and server CPU IP:

Although this is only a general overview of Arm products, it should be noted that there are similarities between Cortex and Neoverse products developed in series at the same time during the design period. Neoverse N1 was developed together with Cortex-A76, so these two microarchitectures can be regarded as brother designs because they have many similarities.

Neoverse V1 can be regarded as the same level design of Cortex-X1, and may share many super-large core structures developed for these two flagship CPUs.

Neoverse N2 is more special because it represents the sibling design of the next-generation Cortex-A core, which is the follow-up product of A78. Arm said that they will get the license for the “Perseus” design before the end of this year, and customers are already using beta RTL, we are likely to hear more about this generation of products at next year’s TechDay event. N2 will be one year behind V1, and it will take more time to see this in the product.

It should be noted that all the above designs are based on Austin and can be regarded as the same microarchitecture family as Cortex-A76. If I remember correctly, the next generation of “Poseidon” design will adopt the new micro-architecture started by Arm’s Sophia-Antipolis design team, although Arm did point out that there is more collaboration and ambiguity between different teams today. . Here, Arm has noticed that the IPC of this generation of design has increased by 30%, and it may be put on the market in 2023.

Undisclosed architecture with SVE: Armv9?

A very notable feature of Neoverse V1 and N2 is that they now support SVE (Scalable Vector Extension), where V1 has two native 256-bit pipelines, and N2 is a 2×128-bit design. The advantage of SVE compared with other SIMD ISAs is that the code written therein can be expanded with changes in the execution width of the microarchitecture, which is impossible for today’s Neon or AVX SIMD instructions.

So far, Fujitsu’s A64FX chip and custom core microarchitecture are the only CPUs announced and can be used with SVE, which means that V1 and N2 will be Arm’s first own designs to actually implement SVE.

Today’s announcement about the contents of the V1 and N2 CPUs has raised more questions, but there is no answer, because the company is unwilling to disclose whether this support involves the first-generation SVE instruction set, or whether they already support SVE2.

In fact, whether it is the Armv8 design or one of the subsequent iterations, the company will not even confirm the designed infrastructure. For the company, this is very unusual, because it has always been transparent in these basic aspects of IP.

I think what’s happening here is that V1 and N2 may both be Armv9 designs, and the company will announce the new ISA iteration at the latest until sometime in the middle of next year. Of course, this is just my own guess, because Arm Declined to comment on this topic.

Update: In fact, it seems that Arm has publicly submitted the upstream initial compiler entry to GCC for Zeus as early as June, confirming that at least Neoverse V1 is Armv8.4 + SVE (1) design. I still think N2 may be a v9 + SVE2 design.

In the final analysis, what we have come to are two extremely compelling new micro-architectures, which have greatly promoted Arm’s position in the infrastructure market. Neoverse N2 is an obvious design that focuses on Arm’s PPA indicators. The company believes that the products designed by customers mainly focus on “horizontal expansion” workloads that require a large number of CPU cores. Here, we can see designs with up to 128 cores.

Neoverse V1 will see a design with a smaller number of cores because of the larger CPU and higher power consumption. Arm believes that the licensee is most likely to adopt a design ranging from 64 to 96. These top products will compete with the best products Intel and AMD can provide, and if performance predictions are achieved (as usually done with Arm), then we will compete fiercely with us I have seen.

SiPearl’s “Rhea” chip is the first public design confirmed to use the new Neoverse V1 core. The chip hopes to have 72 cores in the 7nm TSMC process node. Ampere’s “Siryn” design will also be a candidate for the application of the V1 microarchitecture, which is targeted to be released on TSMC’s 5nm node in 2022.

  

The Links:   NL6448AC33-10 DMF-50840NB-FW

micohuang