2 indicators that should be paid attention to when choosing a clock generator

2 indicators that should be paid attention to when choosing a clock generator

System designers often focus on selecting the most appropriate data converter for the application, and often give less consideration to the selection of the clock-generating device that provides the input to the data converter. However, if the phase noise and jitter performance of the clock generator are not carefully considered, the data converter dynamic range and linearity performance can be severely affected.

System designers often focus on selecting the most appropriate data converter for the application, and often give less consideration to the selection of the clock-generating device that provides the input to the data converter. However, if the phase noise and jitter performance of the clock generator are not carefully considered, the data converter dynamic range and linearity performance can be severely affected.

System Considerations

A typical LTE (Long Term Evolution) base station using a MIMO (Multiple Input Multiple Output) architecture is shown in Figure 1, which consists of multiple transmitters, receivers, and DPD (Digital Predistortion) feedback paths. Various transmitter/receiver components such as data converters (ADC/DAC) and local oscillators (LOs) require a low-jitter reference clock to improve performance. Other baseband components also require clock sources of various frequencies.

2 indicators that should be paid attention to when choosing a clock generator
Figure 1. Clock timing solution for a typical LTE base station with MIMO architecture

The clock source used to achieve synchronization between base stations typically comes from a GPS (Global Positioning System) or CPRI (Common Public Radio Interface) link. This source generally has excellent long-term frequency stability; however, it requires frequency translation to the desired local reference frequency for good short-term stability or jitter. High-performance clock generators perform frequency translation operations and provide low-jitter clock signals that can potentially be distributed to various base station components. Choosing the best clock generator is critical because a poor reference clock increases LO phase noise, which in turn increases transmit/receive EVM (error vector magnitude) and system SNR (signal-to-noise ratio). High clock jitter and noise floor also affect data converters, as it reduces system SNR and causes data converter spurious emissions, further reducing the data converter’s SFDR (spurious free dynamic range). As a result, low-performance clock sources ultimately reduce system capacity and throughput.

Clock Generator Specifications

Although there are various definitions of clock jitter, in data converter applications, the most appropriate definition is phase jitter, which is measured in time domain ps rms or fs rms. Phase jitter (PJBW) is the jitter derived from the integration of the phase noise of the clock signal over a specific offset range of the carrier. The formula is as follows:

2 indicators that should be paid attention to when choosing a clock generator

fCLK is the operating frequency; fMIN/fMAX is the target bandwidth, and S(fCLK) is the SSB phase noise. The upper and lower limits of the integration bandwidth (fMIN/fMAX) are application specific and depend on the relevant spectral components to which the design is sensitive. The designer’s goal is to select a clock generator with the lowest integrated noise or the lowest phase jitter in the desired bandwidth. Traditionally, clock generators have been characterized at 12kHz to 20MHz integration, which is also a specified requirement for optical communication interfaces such as SONET. While this may work for some data converter applications, capturing the associated noise profile of a high-speed data converter sampling clock typically requires a wider integrated spectrum, specifically above 20MHz. When measuring phase noise, the noise is far away from the carrier frequency.

For example, the actual clock frequency used for data converter sampling is generally referred to as being far away from the carrier phase noise. The limit on this noise is often referred to as the phase noise floor, as shown in Figure 2. This figure shows an actual measurement of the ADI HMC1032LP6GE clock generator. The phase noise floor is particularly important in data converter applications because the converter SNR is extremely sensitive to broadband noise at its clock input. When designers evaluate clock generator options, phase noise floor performance must be a key benchmark.

2 indicators that should be paid attention to when choosing a clock generator
Figure 2. Phase noise and jitter performance of the HMC1032LP6GE

In Figure 2, operating at ~160MHz, the integrated phase jitter is ~112fs rms, the integration bandwidth is 12 kHz to 20MHz, and the phase noise floor is ~C168dBc/Hz. It is worth noting here that when choosing the most appropriate clock generator for a data converter, the designer must refer not only to frequency domain phase noise measurements, but also to time domain clock signal quality measurements such as duty cycle , rise/fall time.

Data Converter Performance

To describe the effect of clock noise on the performance of a data converter, consider the converter as a digital mixer with only one slight difference. In the mixer, the phase noise of the LO will be added to the signal being mixed. In a data converter, the phase noise of the clock will be added to the converted output, but is suppressed by the ratio of the signal to clock frequency. Clock jitter can cause sampling time errors that manifest as SNR degradation. (Time jitter (T jitter) is the rms error in the sampling time, in seconds)

In some applications, clock filters may be used to reduce jitter on the clock signal, but this approach has significant drawbacks:

While the filter may remove the wideband noise of the clock signal, the narrowband noise remains the same.
The output of the filter is usually a slow slew rate similar to a sine wave, which affects the susceptibility of the clock signal to noise inside the clock path.
The filter removes the flexibility to change the clock frequency to implement multiple sample rate architectures.

A more practical approach is to maximize the slope of the clock signal with a low noise clock driver with fast slew rate and high output drive capability. This approach can optimize performance for the following reasons:

Eliminating the clock filter reduces design complexity and component count.
The fast rise time suppresses noise inside the ADC clock path.
Both narrowband and wideband noise can be optimized by choosing the best clock source.
Programmable clock generators enable different sampling rates, increasing the flexibility of the solution for different applications.

Ultra-low clock noise floor is critical. Clock jitter noise far from the carrier is sampled in the ADC and superimposed into the ADC’s digital output band. This band is limited by the Nyquist frequency, which is defined as:

2 indicators that should be paid attention to when choosing a clock generator

Clock jitter is typically dominated by the wideband white noise floor of the ADC clock signal. While the SNR performance of an ADC depends on a variety of factors, the effect of wideband jitter on the clock signal is determined by:

2 indicators that should be paid attention to when choosing a clock generator

As shown in the above equation, unlike mixers, the SNR contribution of clock jitter is proportional to the ADC analog input frequency (fIN).

When driving an ADC, clock noise is limited by the bandwidth in the clock driver path, typically dominated by the ADC clock input capacitance. Broadband clock noise modulates the larger input signal and adds to the ADC output spectrum. Phase noise in the clock path degrades output SNR performance proportional to the amplitude and frequency of the input signal. In the worst case, there is a large high frequency signal in the presence of a small signal.

In modern radio communication systems, it is often the case that multiple carrier signals are present at the input and each target signal is then filtered in the DSP to match the signal bandwidth. In many cases, large unwanted signals at one frequency can mix with clock noise, reducing the available SNR at other frequencies in the ADC passband as a result. In this case, the target SNR is the SNR in the desired signal bandwidth. Also, the SNRJITTER values ​​above are actually relative to the amplitude of the largest signal (usually an unwanted or blocking signal).

The output noise in the desired target signal band depends on:

For a given input frequency, calculate the degradation in ADC performance with clock noise and large unwanted signals; for example, calculate the SNR over the full bandwidth of the ADC.
Calculate the SNR in the desired signal bandwidth as the ratio of the desired signal bandwidth to the full bandwidth of the data converter.
Increase this value based on the magnitude of the unwanted signal below full scale.

The result of step b is simply to correct the SNR equation shown earlier in the following way:

2 indicators that should be paid attention to when choosing a clock generator

SNRJITTER: SNR contribution of clock jitter in bandwidth fBW in the presence of a large signal of frequency fin and sampling rate fs.

fIN: The input frequency of the full-scale unwanted signal, in Hz.
TJITTER: The input jitter of the ADC clock, in seconds.
fBW: Bandwidth of desired output signal in Hz.
fs: The sampling rate of the data converter, in Hz.
SNRDC: SNR of the data converter at DC input, in dB

Finally, in the presence of a full-scale blocking signal, the maximum usable SNR in the signal band of interest is simply the sum of the jitter and the DC-contributed noise power.

For example, for a 500MSPS data converter with an ENOB of 12.5 bits (DC) or an SNR of 75dB, the evaluation is performed at 250MHz in a bandwidth equal to half the sampling rate. If the bandwidth of the signal of interest is 5 MHz, the possible SNR at near DC (5MHz bandwidth, perfect clock) is 75+10×log10(250/5)=92 dB.

However, the ADC clock is not perfect; according to Figure 3, the degraded effect in the desired signal bandwidth of 5MHz is a function of the large unwanted signal input at the x-axis frequency. The effect of unwanted signals becomes more severe as jitter increases, and the same is true as input frequency increases. If the magnitude of the unwanted signal decreases, the available SNR will increase proportionally.

2 indicators that should be paid attention to when choosing a clock generator
Figure 3. ADC SNR vs. Clock Jitter and Input Frequency

For example, if a full-scale 5MHz unwanted W-CDMA signal is sampled at a 200MHz input, using a high-quality 500MHz clock (such as the HMC1034LP6GE), and operating in integer mode with 70 fs jitter, the SNR is about 91dB. Conversely, if the clock jitter is reduced to 500fs, the same data converter and signal will only exhibit an SNR of 81dB, which equates to a 10dB drop in performance.

Feeding the same signal into the data converter at 400MHz, a clock of 70fs produces an SNR of 88dB. Similarly, at a clock of 500fs, the SNR value drops to only 75dB.

In summary, choosing the right components for clock generation and data conversion allows you to get the best performance out of a given architecture. Important criteria to consider when selecting a clock generator are phase jitter and phase noise floor, which affect the SNR of the data converter being driven. For the selected clock generator, its low phase noise floor and low integrated phase jitter characteristics help minimize the degradation of SNR performance at higher ADC input frequencies in multicarrier applications.

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